= the two signals of the differential pair. the signals within a given pair may be assigned to either p or n regardless of polarity. 3.8.1.1 general rules for signal pair assignment of analyzer probe the differential pairs that make up the srio links must be assigned to specific pins of the footprint in order to take advantage of the pre-assigned channel assignments provided by nexus when purchasing the srio pre-processor. table 19: 8-channel probe pin assignment pin # signal name pin # signal name 2gnd1cap/tx0 4 cbp/rx0 3 can/tx0 6cbn/rx05 gnd 8 gnd 7 ccp/tx1 10 cdp/rx1 9 ccn/tx1 12 cdn/rx1 11 gnd
3. layout guidelines 67 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com figure 33: analyzer probe pad tracking recommendation 14 gnd 13 cep/tx2 16 cfp/rx2 15 cen/tx2 18 cfn/rx2 17 gnd 20 gnd 19 cgp/tx3 22 chp/rx3 21 cgn/tx3 24 chn/rx3 23 gnd table 19: 8-channel probe pin assignment pin # signal name pin # signal name
3. layout guidelines 68 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com 3.8.2 jtag connectivity the joint test action group (jtag) created the boundary-scan testing standard (documented in the ieee 1149.1 standard ) for testing printed circuit boards (pcbs). the boundary-scan approach involves designing boundary-scan circuitry into the integrated circuit. pcbs populated with 1149.1 compliant devices can be then tested for connectivity, correct device orientation, correct device location, and device identification. all the pins on compliant devices can be controlled and observed using (typically) five pins that are routed to the board edge connector. board designers can develop a standard test for all 1149.1 compliant devices regardless of device manufacturer, package type, technology, or device speed. in addition to the 1149.1 compliant boundary scan tap controller, the tsi578 also contains an 1149.6 compliant tap controller to aid in the production testing of the serdes pins. the tsi578 also has the capability to read and write all internal registers through the jtag interface. through this interface, users may load and modify configuration registers and look up tables without the use of rapidio maintenance transactions or an i 2 c eeprom. please visit the tundra web site at www.tundra.com to download the jtag software to use to access the internal registers. please visit the tundra web site to download the bsdl file for the tsi578. 3.9 reflow profile the tsi578 adheres to jedec-std-020c for its reflow profile. for the leaded version, the peak reflow temperature is 225 o c (+0/-5 o c). for the lead-free version, the peak reflow temperature is 260 o c (+0/-5 o c).
69 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com ? a. clocking this appendix describes device behaviour outside the specified or recommended operating line rates and clock frequencies. the following topics are discussed: ? ?line rate support? on page 69 ? ?p_clk programming? on page 70 a.1 line rate support the tundra tsi578 supports all of the rapidio interconnect specification (revision 1.3) specified line rates of 1.25, 2.50, and 3.125 gbaud. the device also supports line rates that are outside of the rapidio specification. the ability to support multiple line rates gives the tsi578 flexibility in both application support and power consumption. table 20 shows the supported line rates for the tsi578. the serial port select pin, sp_io_speed[1,0] must be set to the values shown in table 20 to achieve the documented line rates. all bit and register settings that are documented for operation with s_clk = 156.25 .mhz also apply to the use of 153.6 mhz and 125 mhz. refer to ?clocking and reset? on page 61 for more clocking information. table 20: tsi578 supported line rates 1 1. this information assumes a +/- 100 ppm clock tolerance that must be obeyed between link partners s_clk_p/n (mhz) baud rate (gbaud) sp_io_speed[1,0] bit settings 153.60 1.2288 0,0 153.60 2.4576 0,1 153.60 3.0720 1,0 156.25 1.2500 0,0 156.25 2.5000 0,1 156.25 3.1250 1,0 125.00 2.5000 1,0
a. clocking 70 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2 p_clk programming the tsi578 recommends a p_clk operating frequency of 100 mhz. however, the device also supports p_clk frequencies less than the recommended 100 mhz. the ability to support other p_clk frequencies gives the tsi578 flexibility in both application support and design. the following sections describe the effects on the tsi578 when the input frequency of the p_clk source is decreased from the recommended 100 mhz operating frequency. a.2.1 rapidio specifications directly affected by changes in the p_clk frequency the following sections describe how changing the p_clk frequency to below the recommended 100 mhz operation affect the counters and state machines in the tsi578 that are defined in the rapidio interconnect specification (revision 1.3) . a.2.1.1 port link time-out csr rapidio part 6: 1x/4x lp-serial physical layer specification revision 1.3: section 6.6.2.2 port link time-out csr (block offset 0x20) the rapidio interconnect specification (revision 1.3) defines the port link time-out csr as follows: the port-link time-out control register contains the time-out timer value for all ports on a device. this time-out is for link events, such as sending a pac ket to receiving the corresponding acknowledge and sending a link-request to receiving the corresponding link-response. the reset value is the maximum time-out interval, and represents between three and six seconds. tundra implementation the tsi578 supports this timer in the ?rio switch port link time out control csr? on page 280 . effects of changing the p_clk frequency are shown in the following formula: ? time-out = 32/f x tval ? f is p_clk frequency in mhz ? tval is the 24-bit counter setting ? maximum tval decimal value of 16,777,215 (0xffffff) the minimum frequency supported by the p_clk input is 25 mhz. operation above 100 mhz or below 25 mhz is not tested or guaranteed.
a. clocking 71 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com effects of changing the p_clk frequency and tval setting can be seen in table 21 . a.2.1.2 rapidio part 6: 1x/4x lp-serial physical layer specification revision 1.3: section 4.7.3.2 state machine variables and functions silence_timer_done the rapidio interconnect specification (revision 1.3) defines the silence_timer_done as follows: asserted when the silence_timer_en has been continuously asserted for 120 +/- 40s and the state machine is in the silent state. the assertion of silence_timer_done causes silence_timer_en to be deasserted. when the state machine is not in the silent state, silence_timer_done is deasserted tundra implementation the tsi578?s silence timer does not have user prog rammable registers. the silence timer is sourced from the p_clk and any changes to p_clk are directly reflected in the timer timeout period. table 21: timer values with p_clk and tval variations p_clk setting tval setting equation timer value 25 mhz 2,343,750 (0x23c346) 32/25 x 2,343,750 3 seconds 25 mhz 4,687,500 (0x47868c) 32/25 x 4,687,500 6 seconds 50 mhz 4,687,500 (0x47868c) 32/50 x 4,687,500 3 seconds 50 mhz 9,375,000 (0x8f0d18) 32/50 x 9,375,000 6 seconds 50 mhz 16,777,215 (0xffffff) 32/50 x 16,777,215 10.4 seconds 100 mhz 9,375,000 (0x8f0d18) 32/100 x 9,375,000 3 seconds 100 mhz 16,777,215 (0xffffff) 32/100 x 16,777,215 5.4 seconds
a. clocking 72 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com discovery_timer_done the rapidio interconnect specification (revision 1.3) defines the discovery_timer_done as follows: asserted when discovery_timer_en has been continuously asserted for 12 +/- 4msec and the state machine is in the discovery state. th e assertion of discovery_timer_done causes discovery_timer_en to be deasserted. when the state machine is not in the discovery state, discovery_timer_done is deasserted. tundra implementation the tsi578?s discovery timer is programmed in the ?rio port x discovery timer? on page 322 . the discovery_timer field is used by serial ports configured to operate in 4x mode. the discovery_timer allows time for the link partner to enter its discovery state, and if the link partner supports 4x mode, for all four lanes to be aligned. the discovery_timer has a default value of 9 decimal, but can be programmed to various values. the results of changing the discovery_timer value and p_clk are shown in table 22 . the discovery_timer field is a 4-bit field whose value is used as a pre-scaler for a 17-bit counter clocked by p_clk. table 22: timer values with discovery_timer and p_clk variations p_clk setting discovery_timer setting equation timer value 100 mhz 9 decimal 9 * 0x1ffff * 1/ p_clk 11.79 ms 100 mhz 9 decimal 9 * 131071 * 1/ p_clk 11.79 ms 25 mhz 1 decimal 1 * 131071 * 1/25 mhz 5.24 ms 25 mhz 2 decimal 2 * 131071 * 1/25 mhz 10.48 ms 25 mhz 15 decimal 15 * 131071 * 1/25 mhz 78.6 ms 50 mhz 1 decimal 1 * 131071 * 1/ 50 mhz 2.62 ms 50 mhz 5 decimal 5 * 131071 * 1/ 50 mhz 13.1 ms 50 mhz 15 decimal 15 * 131071 *1/ 50 mhz 19.7 ms 100 mhz 1 decimal 1 * 131071 * 1/ 100 mhz 1.31 ms 100 mhz 9 decimal 9 * 131071 * 1/ 100 mhz 11.79 ms 100 mhz 15 decimal 15 * 131071 *1/ 100 mhz 19.7 ms
a. clocking 73 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2.1.3 rapidio part 8: rapidio error management extensions specification: section 2.3.2.9 packet time-to-live csr (block offset 0x2c) the rapidio interconnect specification (revision 1.3) defines the packet time-to-live register as follows: the packet time-to-live register specifies the length of time that a packet is allowed to exist within a switch device. the maximum value of the time-to-live variable (0xffff) shall correspond to 100 msec. +/-34%. the resolution (minimum step size) of the time-to-live variable shall be (maximum value of time-to-live)/(2e16-1). the reset value is all logic 0s, which disables the time-to-live function so that a packet never times out. this register is not required for devices without switch functionality. tundra implementation the tsi578?s ?rio packet time-to live csr? on page 303 specifies the length of time that a packet is allowed to exist within a switch device. the maximum value of the time-to-live variable (0xffff) corresponds to 100 msec +/-34%. the resolution (minimum step size) of the time-to-live variable is: ? (maximum value of time-to-live)/(2e16-1). due to the uncertainty of the arrival of a packet relative to clock edges, a packet?s time to live expiry time is not precise, but falls within a range. the range is as follows: ? minimum time-to-live ns = {1/p_clk x 132} x ttlval ? maximum time-to-live ns = {1/p_clk x 198} x ttlval the ttl field in the ?rio packet time-to live csr? on page 303 is a 16-bit counter with a maximum decimal value of 65535. table 23 shows the ttl counter values using different values for p_clk. the default value of ttl is 0, which disables the time-to-live counter. table 23: ttl values with p_clk variations p_clk setting equation timer value 25 mhz minimum time-to-live ns = {1/25mhz x 132} x 1 5.28 us {1/25mhz x 132} x 15782 (3da6) 83.3 ms {1/25mhz x 198} x 15782 (3da6) 124.9 ms minimum time-to-live ns = { 1/25mhz x 198} x 65535 519 ms
a. clocking 74 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com 50 mhz minimum time-to-live ns = {1/50mhz x 132} x 1 10.56 us {1/50mhz x 132} x 31566 (7b4e) 83.3 ms {1/50mhz x 198} x 31566 (7b4e) 125 ms maximum time-to-live ns = {1/50mhz x 198} x 65535 259.5 ms 100 mhz minimum time-to-live ns = {1/100mhz x 132} x 1 132 ns {1/100mhz x 132} x 63132 (f69c) 83.3 ms {1/100mhz x 198} x 63132 (f69c) 125 ms maximum time-to-live ns = {1/100mhz x 198} x 65535 = 129.8 ms table 23: ttl values with p_clk variations p_clk setting equation timer value
a. clocking 75 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2.2 tundra specific timers the following sections describe how changing the p_clk frequency to below the recommended 100 mhz operation affect the tundra-specific counters and state machines in the tsi578. a.2.2.1 dead link timer the dead link timer period is controlled by the dlt_thresh field in the ?srio mac x digital loopback and clock selection register? on page 403 . each time a silence is detected on a link, the counter is reloaded from this register and starts to count down. when the count reaches 0, the link is declared dead, which means that all packets are flushed from the transmit queue and no new packets are admitted to the queue until the link comes up. the duration of the dead link timer is computed by the following formula: ? 2^^13 * dlt_thresh * p_clk period ? p_clk is 100mhz (which gives a p_clk period of 10ns) ? default value of dlt_thresh is 0x7fff (which corresponds to 32767) ? using these parameters, the populated formula is 8192*32767*10e-9 = 2.68 seconds when enabled, this timer is used to determine when a link is powered up and enabled, but dead (that is, there is no link partner responding). when a link is declared dead, the transmitting port on the tsi578 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue. the dlt_thresh is a 15-bit counter with a maximum value of 32767. table 24 shows equations using different values for dlt_thresh and p_clk. table 24: timer values with p_clk and dlt_thresh variations p_clk setting equation timer value 25 mhz 8192 * 1 * 1/25 mhz 327 us 8192 * 32767 * 1/25 mhz 10.74 seconds 50 mhz 8192 * 1 * 1/50 mhz 163.8 us 8192 * 32767 * 1/50 mhz 5.37 seconds 100 mhz 8192 * 1 * 1/100mhz 81.9 us 8192 * 32767 * 1/100mhz 2.68 seconds
a. clocking 76 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2.3 i 2 c interface and timers the i 2 c interface clock is derived from the p_clk. decreasing the frequency of p_clk causes a proportional decrease in the i 2 c serial clock and affects the i 2 c timers. the timer values can be re-programmed during boot loading but the changes does not take effect until after the boot load has completed. as a result, a decrease from 100 mhz to 50 mhz of p_clk causes a doubling of the boot load time of the eeprom. once boot loading has completed, the new values take effect and the i 2 c interface can operate at the optimum rate of the attached devices. a.2.3.1 i 2 c time period divider register the ?i2c time period divider register? this register provides programmable extension of the reference clock period into longer periods used by the timeout and idle detect timers. usdiv period divider for micro-second based timers the usdiv field divides the reference clock down for use by the idle detect timer, the byte timeout timer, the i2c_sclk low timeout timer, and the milli-second period divider. ? period(usdiv) = period(p_clk) * (usdiv + 1) ? p_clk is 10 ns ? tsi578 reset value is 0x0063 msdiv period divider for milli-second based timers the msdiv field divides the usdiv period down further for use by the arbitration timeout timer, the transaction timeout timer, and the boot/diagnostic timeout timer. ? period (msdiv) = period(usdiv) * (msdiv + 1) ? tsi578 reset value is 0x03e7 a.2.3.2 i2c start condition setup/hold timing register the ?i2c start condition setup/hold timing register? programs the setup and hold timing for the start condition when generated by the master control logic. the timer periods are relative to the reference clock. this register is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current eeprom. start_setup count for the start condition setup period the start_setup field defines the minimum setup time for the start condition; that is, both i2c_sclk and i2c_sd seen high prior to i2c_sd pulled low. this is a master-only timing parameter. ? period (start_setup) = (start_setup * period(pclk)) ? pclk is 10ns tip this value also doubles as the effective stop hold time.
a. clocking 77 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com ? reset time is 4.71 microseconds. ? tsi578 reset value is 0x01d7 start_hold count for the start condition hold period the start_hold field defines the minimum hold time for the start condition; that is, from i2c_sd seen low to i2c_sclk pulled low. this is a master only timing parameter. ? period (start_hold) = (start_hold * period(p_clk)) ? p_clk is 10 ns ? reset time is 4.01 microseconds ? tsi578 reset value is 0x0191 a.2.3.3 i2c stop/idle timing register the ?i2c stop/idle timing register? programs the setup timing for the stop condition when generated by the master control logic and the idle detect timer. the stop/idle register is broken down as follows: ? the timer period for the stop_setup is relative to the reference clock ? the timer period for the idle detect is relative to the usdiv period ? the stop_setup time is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current eeprom. stop_setup count for stop condition setup period the stop_setup field defines the minimum setup time for the stop condition (that is, both i2c_sclk seen high and i2c_sd seen low prior to i2c_sd released high). this is a master-only timing parameter. ? period(stop_setup) = (stop_setup * period(p_clk)) ? p_clk is 10ns ? reset time is 4.01 microseconds ? tsi578 reset value is 0x0191 tip the start_setup time doubles as the stop hold.
a. clocking 78 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com idle_det count for idle detect period the idle_det field is used in two cases. first, it defines the period after reset during which the i2c_sclk signal must be seen high in order to call the bus idle. this period is needed to avoid interfering with an ongoing transaction after reset. second, it defines the period before a master transaction during which the i2c_sclk and i2c_sd signals must both be seen high in order to call the bus idle. this period is a protection against external master devices not correctly idling the bus. ? period(idle_det) = (idle_det * period(usdiv)), where usdiv is the microsecond time defined in the ?i2c time period divider register? ? reset time is 51 microseconds ? tsi578 reset value is 0x0033 a.2.3.4 i2c_sd setup and hold timing register the ?i2c_sd setup and hold timing register? programs the setup and hold times for the i2c_sd signal when output by either the master or slave interface. it is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current eeprom. sda_setup count for the i2c_sd setup period the sda_setup field defines the minimum setup time for the i2c_sd signal; that is, i2c_sd is set to a desired value prior to rising edge of i2c_sclk. this applies to both slave and master interface. ? period(sda_setup) = (sda_setup * period(p_clk)), where p_clk is 10ns. ? reset time is 1260 nanoseconds ? tsi578 reset value is 0x007e sda_hold count for i2c_sd hold period the sda_hold field defines the minimum hold time for the i2c_sd signal; that is, i2c_sd valid past the falling edge of i2c_sclk. this applies to both slave and master interface. ? period(sda_hold) = (sda_hold * period(p_clk)), where p_clk is 10 ns. ? reset time is 310 nanoseconds ? tsi578 reset value is 0x001f a value of zero results in no idle detect period, meaning the bus will be sensed as idle immediately. this value should be set to the sum of the i2c_sd setup time and the maximum rise/fall time of the i2c_sd signal in order to ensure that the signal is valid on the output at the correct time. this time is different than the raw i2c_sd setup time in the i 2 c specification .
a. clocking 79 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2.3.5 i2c_sclk high and low timing register the ?i2c_sclk high and low timing register? programs the nominal high and low periods of the i2c_sclk signal when generated by the master interface. it is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current eeprom. scl_high count for i2c_sclk high period the scl_high field defines the nominal high period of the clock, from rising edge to falling edge of i2c_sclk. this is a master-only parameter. the actual observed period may be shorter if other devices pull the clock low. ? period(scl_high) = (scl_high * period(p_clk)) ? p_clk is 10 ns ? reset time is 5.00 microseconds (100 khz) ? tsi578 reset value is 0x01f4 scl_low count for i2c_sclk low period the scl_low field defines the nominal low period of the clock, from falling edge to rising edge of i2c_sclk. this is a master-only parameter. the actual observed period may be longer if other devices pull the clock low. ? period(scl_low) = (scl_low * period(p_clk)) ? p_clk is 10 ns ? reset time is 5.00 microseconds (100 khz) ? tsi578 reset value is 0x01f4 a.2.3.6 i2c_sclk minimum high and low timing register the ?i2c_sclk minimum high and low timing register? programs the minimum high and low periods of the i2c_sclk signal when generated by the master interface. it is shadowed during boot loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the current eeprom. scl_minh count for i2c_sclk high minimum period the scl_minh field defines the minimum high period of the clock, from rising edge seen high to falling edge of i2c_sclk. this is a master-only parameter. the actual observed period may be shorter if other devices pull the clock low. ? period(scl_minh) = (scl_minh * period(p_clk)) ? p_clk is 10 ns ? reset time is 4.01 microseconds ? tsi578 reset value is 0x0191
a. clocking 80 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com scl_minl count for i2c_sclk low minimum period the scl_minl defines the minimum low period of the clock, from falling edge seen low to rising edge of i2c_sclk. this is a master-only parameter. the actual observed period may be longer if other devices pull the clock low. ? period(scl_minl) = (scl_minl * period(p_clk)) ? p_clk is 10 ns ? reset time is 4.71 microseconds ? tsi578 reset value is 0x01d7 a.2.3.7 i2c_sclk low and arbitration timeout register the ?i2c_sclk low and arbitration timeout register? programs the i2c_sclk low timeout and the arbitration timeout. the arbitration timer period is relative to the msdiv period, and the i2c_sclk low timeout period is relative to the usdiv period. scl_to count for i2c_sclk low timeout period the scl_to field defines the maximum amount of time for a slave device holding the i2c_sclk signal low. this timeout covers the period from i2c_sclk falling edge to the next i2c_sclk rising edge. a value of 0 disables the timeout. ? period(scl_to) = (scl_to * period(usdiv)) ? usdiv is the microsecond time defined in the ?i2c time period divider register? . ? the reset value of this timeout is 26 milliseconds ? tsi578 reset value is 0x65bb arb_to count for arbitration timeout period the arb_to field defines the maximum amount of time for the master interface to arbitrate for the bus before aborting the transaction. this timeout covers the period from master operation start (see setting the start bit in the ?i2c master control register? ) until the ack/nack is received from the external slave for the slave device address. a value of 0 disables the timeout. ? period(arb_to) = (arb_to * period(msdiv)) ? msdiv is the millisecond time defined in ?i2c time period divider register? . ? the reset value of this timeout is 51 milliseconds ? this timeout is not active during the boot load sequence. ? tsi578 reset value is 0x0033
a. clocking 81 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com a.2.3.8 i2c byte/transaction timeout register the ?i2c byte/transaction timeout register? programs the transaction and byte time-outs. the timer periods are relative to the usdiv period for the byte timeout, and relative to the msdiv period for the transaction timeout. byte_to count for byte timeout period the byte_to field defines the maximum amount of time for a byte to be transferred on the i 2 c bus. this covers the period from start condition to next ack/nack, between two successive ack/nack bits, or from ack/nack to stop/restart condition. a value of 0 disables the timeout. ? period(byte_to) = (byte_to * period(usdiv)) ? usdiv is the microsecond time defined in ?i2c time period divider register? . ? this timeout is disabled on reset, and is not used during boot load. ? tsi578 reset value is 0x0000 tran_to count for transaction timeout period the tran_to field defines the maximum amount of time for a transaction on the i2c bus. this covers the period from start to stop. a value of 0 disables the timeout. ? period(tran_to) = (tran_to * period(msdiv)) ? msdiv is the millisecond time defined in ?i2c time period divider register? . ? this timeout is disabled on reset, and is not used during boot load ? tsi578 reset value is 0x0000 a.2.3.9 i2c boot and diagnostic timer the ?i2c boot and diagnostic timer? programs a timer used to timeout the boot load sequence, and can be used after boot load as a general purpose timer. count count for timer period the count field defines the period for the timer. the initial reset value is used for overall boot load timeout. a value of 0 disables the timeout. the timer begins counting when this register is written. if this register is written while the counter is running, the timer is immediately restarted with the new count, and the dtimer/blto event is not generated. when the timer expires, either the blto or dtimer event is generated, depending on whether the boot load sequence is active. if freerun is set to 1 when timer expires, then the timer is restarted immediately (the event is still generated), providing a periodic interrupt capability. ? period(dtimer) = (count * period(msdiv)) tip during normal operation, this timer can be used for any general purpose timing.
a. clocking 82 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com ? msdiv is the millisecond period define in ?i2c time perioddivider register? . ? the reset value for the boot load timeout is four seconds. if the boot load completes before the timer expires, the timer is set to zero (disabled). ? tsi578 reset value is 0x0fa0 a.2.4 other performance factors this section describes any other factors that may impact the performance of the tsi578 if p-clk is programmed to operate lower than the recommended 100 mhz frequency. a.2.4.1 internal register bus operation the internal register bus, where all the internal registers reside, is a synchronous bus clocked by the p_clk source. a decrease in the p_clk frequency causes a proportional increase in register access time during rapidio maintenance transactions, jtag registers accesses, and i 2 c register accesses. rapidio maintenance transaction maintenance transactions use the internal register bus to read and write registers in the tsi578. if the p_clk frequency is decreased, it may be necessary to review the end point?s response latency timer value to ensure that it does not expire before the response is returned. jtag register interface changing the p_clk frequency affects accesses to the internal registers through the jtag register interface because the interface uses the internal regi ster bus. however, since access to the registers using the jtag interface is largely a manual command line terminal operation using the tundra jtag register interface software (see www.tundra.com for more information), the decreased performance will not be perceivable. boundary scan operations are not affected by a chance in the p_clk frequency because these transactions use the jtag tck clock signal and do not access the internal register bus. changing the frequency of the p_clk does not affect the operation or performance of the rapidio portion of the switch, in particular its ability to route or multicast packets between ports.
83 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com ? b. ordering information this chapter discusses ordering information and describes the part numbering system for the tsi578. b.1 ordering information when ordering the tsi578 please refer to the device by its full part number, as displayed in table 25 . b.2 part numbering information the tundra part numbering system is explained as follows. ? ( ) ? indicates optional characters. ? tsi ? tundra system interconnect product identifier. all tundra semiconductor product numbers start with ?tsi.? ? nnnn ? product number (may be three or four digits). ? ss(s) ? maximum operating frequency or data transfer rate of the fastest interface. for operating frequency numbers, m and g represent mhz and ghz. for transfer rate numbers, m and g represent mbps and gbps. table 25: tsi578 ordering information part number frequency temperature package pin count tsi578-10gcl 1.25 - 3.125 gbit/s commercial fcbga 675 tsi578-10gcly 1.25 - 3.125 gbit/s commercial fcbga (rohs) 675 tsi578-10gil 1.25 - 3.125 gbit/s industrial fcbga 675 TSI578-10GILY 1.25 - 3.125 gbit/s industrial fcbga (rohs) 675 tsi nnn(n) - ss(s) e p g (z#) tundra product identifier product number operating frequency operating environment package type prototype version status rohs/green compliance
b. ordering information 84 tsi578 hardware manual 80b803a_ma002_07 tundra semiconductor corporation www.tundra.com ? e ? operating environment in which the product is guaranteed. this code may be one of the following characters: ? c - commercial temperature range (0 to +70c) ? i - industrial temperature range (-40 to +85c) ? e - extended temperature range (-55 to +125c) ? p ? the package type of the product: ? b - ceramic ball grid array (cbga) ? e, l, j, and k - plastic ball grid array (pbga) ? g - ceramic pin grid array (cpga) ? m - small outline integrated circuit (soic) ? q - plastic quad flatpack ? g ? tundra products fit into three rohs-compliance categories: ? y - rohs compliant (6of6) ? these products contain none of the six restricted substances above the limits set in the eu directive 2002/95/ec. ? y - rohs compliant (flip chip) ? these products contain only one of the six restricted substances: lead (pb). these flip-chip products are rohs compliant through the lead exemption for flip chip technology, commission decision 2005/747/ec, which allows lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit flip chip packages. ? v - rohs compliant/green - these products follow the above definitions for rohs compliance and meet jig (joint industry guide) level b requirements for brominated flame retardants (other than pbbs and pbdes). ? z# ? prototype version status (optional). if a product is released as a prototype then a ?z? is added to the end of the part number. further revisions to the prototype prior to production release would add a sequential numeric digit. for example, the first prototype version of device would have a ?z,? a second version would have ?z1,? and so on. the prototype version code is dropped once the product reaches production status.